1. Field of the Invention
The present invention relates to a mounting technique of a semiconductor device, particularly to a wiring structure of a base material on which a semiconductor device is directly or indirectly mounted, and a connection structure between a semiconductor device and a base material or between the base materials.
2. Description of the Related Art
Several techniques concerning a wiring structure of a base material (substrate) on which a semiconductor device (semiconductor chip) is directly or indirectly mounted have heretofore been proposed. These techniques have been described, for example, in Jpn. Pat. Appln. KOKAI Publication Nos. 7-115112, 8-70024, 9-129673 and the like.
In a general semiconductor device, a semiconductor chip is directly mounted on one main surface (chip mounting surface) of a double-surface wiring substrate on whose opposite main surfaces wirings are formed. A plurality of chip connection wirings electrically connected to the semiconductor chip are formed on the chip mounting surface of the substrate. Chip connection pads for a plurality of electrode pads formed on the semiconductor chip are formed on the respective chip connection wirings. Each electrode pad is bonded to each chip connection pad, and the semiconductor chip is electrically connected to each chip connection wiring. An external wiring (external terminal) for electrically connecting the semiconductor chip to another substrate, electric component or the like is formed on the other main surface (chip non-mounting surface) of the substrate.
Since a connection density of the semiconductor chip to a wiring substrate is high in the wiring substrate having the above-described wiring structure, a need for miniaturization and multilayer of the wiring substrate easily arises. The wirings or the terminals need to be formed on the opposite main surfaces of the wiring substrate. Therefore, a manufacturing cost of the wiring substrate easily increases. Additionally, the manufacturing cost of the semiconductor device provided with this wiring substrate easily increases. In the method of connecting the semiconductor chip to the wiring substrate, a large stress is easily applied onto a connection portion between the semiconductor chip and the wiring substrate, the surface of the semiconductor chip or the like because of a difference in coefficient of thermal expansion between the chip and substrate. Especially, when a brittle low-k film is used in an interlayer insulating film in the semiconductor chip, there is a high possibility that fatal defects such as peeling of the interlayer insulating film are caused by the stress applied onto the semiconductor chip. That is, there is a high possibility that durability, reliability, capability, quality and the like of the semiconductor device are deteriorated.